/****************************************************************************************/
/*                                                                     					*/
/*  M16C/62P Group Program Collection                                  					*/
/*                                                                     					*/
/*  FILE NAME : lowlevelinit.c                                       					*/
/*  CPU       : This program is the Serial flash boot loader by Xmodem data transfer	*/
/*  HISTORY   : 2006.12.08 Ver 0.01                                    					*/
/*                                                                    	 				*/
/*  Copyright (C) 2006. Renesas Technology Corp.                       					*/
/*  Copyright (C) 2006. Renesas Solutions Corp.                        					*/
/*  All right reserved.                                                					*/
/*                                                                     					*/
/*****************************************************************************************/

/**************************************/
/*    include file                    */
/**************************************/
#include"sfr62p.h"

#include "lowlevelinit.h"

/**************************************/
/*    __low_level_init function       */
/**************************************/
void __low_level_init(void)
{

//	low_level_init is called as part of CSTARTUP

//  NOTE: PLL register bits PLC02 -> PLC00 can only be set once after reset. 
//	This is set up for 24MHz operation running off a 6MHz crystal.

//
	static unsigned long pll_wait = 0;


	// In the event of 'program runaway', the PRCR (Protect Register) will try and restrict access 
	// to the following registers:
	// CM0 - System Clock Control Register 0
	// CM1 - System Clock Control Register 1
	// CM2 - Oscillation Stop Detection Register
	// PLC0 - PLL Control Register 0
	// PCLKR - Peripheral Clock Select Register
	// PM0 - Processor Mode Register 0
	// PM1 - Processor Mode Register 1
	// PM2 - Processor Mode Register 2
	// TB2SC - Timer B2 Special Mode Register
	// INVC0 - Three Phase PWM Control Register 0 
	// INVC1 - Three Phase PWM Control Register 1
	// PD9 - Port 9 Direction Register
	// S3C - Serial I/O Control Register 3
	// S4C - Serial I/O Control Register 4
	// VCR2 - Voltage Detection Register 2
	// D4INT - Voltage Down Detection Interrupt Register
	
	// PRCR - Protect Register
	//-------------------------------------------------------------------------
	prc3 = 1;				// 0 - Write Protected	: VCR2, D4INT
							// 1 - Write Enabled	: VCR2, D4INT
					

	prc2 = 1;				// 0 - Write Protected	: PD9, S3C, S4C
							// 1 - Write Enabled	: PD9, S3C, S4C
	

	prc1 = 1;				// 0 - Write Protected	: PM0, PM1, PM2, TB2SC, INV0, INVC1
							// 1 - Write Enabled	: PM0, PM1, PM2, TB2SC, INV0, INVC1
	
 
	prc0 = 1;				// 0 - Write Protected	: CM0, CM1, CM2, PLC0, PCLKR
							// 1 - Write Enabled	: CM0, CM1, CM2, PLC0, PCLKR
	


	// PM0 - Processor Mode Register 0
	//-------------------------------------------------------------------------
	pm07 = 1;				// 0 - BCLK is output
  							// 1 - BCLK is not output (Pin is high impdance)
 	

	pm06 = 1;				// 0 - Port 4.0 -> Port 4.3 are Address Pins
  							// 1 - Port 4.0 -> Port 4.3 are Port Pins
					

	pm05 = 0;				//	PM05	PM04
					

	pm04 = 0;				// 	0 		0		- Multiplexed bus is unused
  							// 	0		1 		- Allocated to /CS2 space
  							// 	1		0		- Allocated to /CS1 space
  							// 	1		1		- Allocated to entire /CS space
					
	pm03 = 0;				// Software Reset Bit
  							// Setting this bit to '1' resets the micro
					
		

	
	pm02 = 0;				// Only valid in Memory Expansion or Microprocessor
  							// 0 - /RD, /BHE, /WR
  							// 1 - /RD, /WRH, /WRL
							/*/RD, /BHE, /WR*/

	
	pm01 = 0;				//	PM01	PM00
					

	
	pm00 = 0;				// 	0 		0		- Single Chip Mode
							// 	0 		1		- Memory Expansion Mode
  							// 	1 		0		- MUST NOT BE SET
  							// 	1 		1		- Microprocessor mode
  							 	
	// PM1 - Processor Mode Register 1
	//-------------------------------------------------------------------------  	
	pm17 = 0;				// 0 - No wait state
							// 1 - 1 wait state
 
  							
	pm15 = 0;				// 	PM15	PM14
	


	pm14 = 0;				// 	0 		0		- 1 Mbyte Mode
							// 	0		1 		- MUST NOT BE SET
  							// 	1		0		- MUST NOT BE SET
  							// 	1		1		- 4 Mbyte Mode

	pm13 = 1;				// Internal Addresses
 							// 0 - 	RAM:	H'400 -> H'3FFF accessable
  							//		ROM:	H'D000 -> H'FFFFF accessable
  							// 1 - 	RAM:	Entire area is accessable
  							//		ROM:	Entire area is accessable
  							// External Addresses
  							// 0 -	RAM:	H'4000 -> H'7FFFF are accessable
  							//		ROM:	H'80000 -> H'CFFFF are accessable
  							// 1 -	RAM:	H'4000 -> H'7FFFF are reserved
  							//		ROM:	H'80000 -> H'CFFFF are reserved
	
	pm12 = 0;				// 0 - Watchdog Generates Interrupt
							// 1 - Watchdog Resets Device

	pm11 = 1;				// 0 - Port 3.4 -> Port 3.7 are Address Pins
							// 1 - Port 3.4 -> Port 3.7 are Port Pins
 
	pm10 = 1;				// 0 - H'8000 -> H'26FFF (Block A) Disabled
							// 1 - H'8000 -> H'26FFF (Block A) Enabled
  							
	// CM1 - System Clock Control Register 1
	//-------------------------------------------------------------------------
	cm17 = 0;				// Main Clock Divide Ratio
					

	
	cm16 = 0;			  	//	CM17	CM16
							//	0		0		- No Division
							//	0		1		- Divide by 2
							//	1		0		- Divide by 4
							//	1		1		- Divide by 16

	cm15 = 1;				// 0 - Xin - Xout Drive Capacity LOW						
							// 1 - Xin - Xout Drive Capacity HIGH

						
	cm11 = 0;				// 0 - System Clock is Main Clock
	
						  	// 1 - System Clock is PLL Clock

	cm10 = 0;				// 0 - Clock ON
	
						  	// 1 - ALL Clocks OFF
	
	// CM0 - System Clock Control Register 0
	//-------------------------------------------------------------------------
	cm07 = 0;				// 0 - System Clock is Main Clock, PLL Clock or Ring Oscillator Clock
							// 1 - System Clock is Sub Clock

	cm06 = 0;				// 0 - Main Clock is set by bit CM17 & CM16 in Register, CM1
							// 1 - Main Clock is divided by 8

	cm05 = 0;				// 0 - Main Clock is ON	
							// 1 - Main Clock is OFF

	cm04 = 0;				// 0 - Pins P8.6 & P8.7 are I/O pins
							// 1 - Pins P8.6 & P8.7 are Sub Clock Oscillator pins

	cm03 = 1;				// 0 - XCin - XCout Drive Capacity LOW						
	
						  	// 1 - XCin - XCout Drive Capacity HIGH
						  	
	cm02 = 0;				// 0 - DO NOT stop peripheral function clock in wait mode
							// 1 - Stop peripheral function clock in wait mode

	cm01 = 0;				// Clock Output Selection
	

	cm00 = 0;				//	CM01	CM00
							//	0		0		- P5.7 is I/O Port
							//	0		1		- fc is Output: Main Clock, PLL Clock or Ring Oscillator Clock
							//	1		0		- f8 is Output: fc / 8
							//	1		1		- f32 is Output: Sub Clock / 32
  	
	// CM2 - Oscillation Stop Detection Register
	//-------------------------------------------------------------------------
	cm27 = 0;				// After Oscillation Stop & re-oscillation detected
	
  							// 0 - Oscillation stop detection RESET
  							// 1 - Oscillation stop detection INTERRUPT

	// PLC0 - PLL Control Register 0
	//-------------------------------------------------------------------------
	plc07 = 0;				// 0 - PLL OFF
							// 1 - PLL ON
	
	plc02 = 0;				// PLL Multiplying Factor
					

	plc01 = 1;				//	PLC02	PLC01	PLC00
					
	
	plc00 = 0;				//	0		0		0		- DO NOT SET	
 							//	0		0		1		- Multiplier x 2
 							//	0		1		0		- Multiplier x 4
 							//	0		1		1		- Multiplier x 6
 							//	1		0		0		- Multiplier x 8
 							//	1		0		1		- DO NOT SET
 							//	1		1		0		- DO NOT SET
 							//	1		1		1		- DO NOT SET

	// PM2 - Processor Mode Register 2
	//-------------------------------------------------------------------------
	pm22 = 0;			// 0 - WDT Clock Source is CPU clock
						// 1 - WDT Clock Source is RING Oscillator

	pm21 = 0;			// 0 - Clock settings are protected by PRCR register
						// 1 - Clock modification is disabled
						// NOTE: 	Once this bit is set to '1', it can not be cleared to '0' by software.
						// 			Once this bit is set to '1', writing to the following has no effect
						//			CM02 bit of CM0 register
						//			CM05 bit of CM0 register (main clock does not stop)
						//			CM07 bit of CM0 register (clock source for the CPU clock does not change)
						//			CM10 bit of CM1 register (stop mode is not entered)
						//			CM11 bit of CM1 register (clock source for the CPU clock does not change)
						//			CM20 bit of CM2 register (oscillation stop, re-oscillation detection function settings do not change)
						//			All bits of PLC0 register (PLL frequency synthesizer settings do not change)

	pm20 = 0;			// 0 - '2' waits required when accessing PLL SFR
						// 1 - '1' waits required when accessing PLL SFR

  	// Turn PLL ON
	plc07 = 1;			// 0 - PLL OFF
						// 1 - PLL ON

	// Wait until the PLL clock becomes stable (tsu(PLL))
	for( pll_wait = 0 ; pll_wait < 119760 ; pll_wait++ );

  	// Set the PLL clock as the CPU clock source               	
	cm11 = 1;		// 0 - System Clock is Main Clock
				  	// 1 - System Clock is PLL Clock

}
